The invention pertains to a partial response maximum likelihood (PRML) bit detection apparatus for deriving a bit sequence from an input information signal, comprising
input means for receiving the input information signal,
sampling means for sampling, at a predetermined sampling frequency, the input information signal at sampling instants ti so as to obtain sample values of the input information signal at said sampling instants ti, said sampling frequency having a relationship with a bit frequency,
calculating means for
(a) calculating at a sampling instant ti for one or more of a plurality of states sj at said sampling instant, an optimum path metric value PM(sj,ti) and for determining for each of said one or more states a best predecessor state at the directly preceding sampling instant tnxe2x88x921, a state at said sampling instant identifying a sequence of n subsequent bits,
(b) establishing the best path from the state at the said sampling instant ti having the lowest optimum path metric value, back in time towards the sampling instant tixe2x88x92N via best predecessor states, established earlier for earlier sampling instants, to establish an optimum state at said sampling instant tixe2x88x92N,
(c) outputting at least one bit of said n bits of the sequence of bits corresponding to said established optimum state at said sampling instant tixe2x88x92N,
(d) repeating said steps (a) to (c) for a subsequent sampling instant ti+1.
A bit detection apparatus according to the introductory paragraph is widely used in magnetic, magneto-optical and optical recording systems. These systems usually employ modulation codes with a d constraint. This constraint stipulates that runs of ones and zeros in the RLL channel bitstream be at least d+1 symbol intervals long. The value d=2 is used, for example, in compact disc (CD) and digital versatile disc (DVD) systems, while d=1 is encountered in magneto-optical recording and the new rewritable DVR-format. Among other advantages, the d constraint limits intersymbol interference (ISI), thereby facilitating equalization and bit detection. As a result, early reception schemes for CD could generally get by with a fixed prefilter for noise suppression and equalization, and a memoryless slicer for bit detection [1]. More recent optical recording systems, like CD-R, CD-RW, D-VCD, DVD, and especially DVR and other formats succeeding DVD, exhibit smaller mechano/optical tolerances than CD, and as a result parameter variations, noise, cross-talk from neighboring tracks, and ISI tend to become more severe. Because of these developments, an increasing interest can be discerned in reception schemes that can handle this mixture of artifacts in a near-optimum fashion [2],[3],[4],[5],[6]. Schemes of this kind are generally built around a Viterbi detector, which is based on a Finite State Machine (FSM) or trellis, that is tailored to the d constraint. The states of the FSM correspond one to one with the allowed sequences of a predetermined length n of channel bits that are compatible with the d-constraint. Attainable operating speed of such detectors is limited by their add-compare-select (ACS) loop, and may not be compatible with the rapidly increasing bit rates of PC-related recording systems, such as CD-ROM and DVD-ROM, and like developments in bit rates for the new emerging video recording formats such as DVR.
It is an object of the present invention to provide a detection apparatus according to the opening paragraph, which allows for a reliable bit detection and which yet has a high operating speed. According to the invention the detection apparatus is characterized in that mutually complementary sequences of n subsequent bits are allocated to the same state. A high operating speed is attained through a substantial detector simplification. This simplification is based on the recognition that the key difficulty at hand is that of pinpointing the location of recorded transitions. The polarity of the signal between transitions, by comparison, is literally visible xe2x80x98at a glancexe2x80x99, and reliable polarity detection comes almost for free.
The detection apparatus according to the invention is very suitable for deriving a bit sequence ({circumflex over (x)}k) from an input information signal according to a runlength limited code. In that case, as claimed in claim 2 preferably n is equal to the minimum allowed runlength of said code. By exploiting this fact, the state diagram underlying the detector can be collapsed to contain only a single non-transient state, and the detection process can be reformulated in terms of difference metrics, as claimed in claim 3. All paths share this state. The resulting critical loop involves one addition and a binary selection, while digital word lengths within the loop can be unusually small (e.g. 3 or 4 bits). These features permit a very high operating speed.
The path metric may be calculated on the basis of a partial response of a duration longer than the minimum runlength plus 1 (or, longer than d+2). In that case one or more bits preceding the sequence of bits relevant to a state transition have to be determined by an auxiliary method, e.g. by local sequence feedback as described in claim 4, or by threshold detection described in claim 5 or by runlength pushback detection described in claim 6.